Almost all of the applications of analog memories to date have been in high energy physics colliders. In these applications, large arrays of analog memories are embodied in MOS semiconductor electronics, and comprise part of the front-end electronics for the collider detectors.
A switched-capacitor analog memory (SCAM), or switched-capacitor storage array, is an array of cells in which analog samples from a single input channel can be stored at successive time intervals. Each cell of the SCAM comprises a single capacitor and a switch. The storage cells are individually addressable during write and read operations by control logic which provides a pointer to activate a particular cell switch at the appropriate time.
An analog-to-digital converter (ADC) is usually connected to the analog memory to change the analog output to digital form. Each ADC has two inputs, the signal input which connects to the SCAM, and the reference input, to which a fixed known reference voltage or current such as an error correction or other offset is applied. In operation, the ADCs carry out their conversion based on the value of the reference level they receive.
A high energy physics collider such as the Relativistic Heavy Ion Collider (RHIC) uses thousands of detector channels to capture data at successive 110 nanosecond time intervals. Large arrays of switched-capacitor analog memories may be chosen as part of the large data acquisition system for RHIC. A general representation of a SCAM array is shown in FIG. 1. In FIG. 1, the array 11 comprises multiple channels 12 of switched-capacitor analog memories 14, 15, etc. FIG. 1 also depicts at 13 an array comprising an equal number of analog-to-digital converters 16, 17, etc., connected to the analog memory channels in the standard way.
In FIG. 1, analog inputs from the signal sources (detector preamplifiers in the example of RHIC) are input on respective SCAM 14, 15, etc., signal input leads 18, 19, etc. Control logic (not shown) to each SCAM 14, 15 etc., causes those cells 28 that are in the first column (column 26) to capture (store) the instantaneous values of all the respective input signals at a time, say t.sub.0. At increasing time t.sub.1, about 110 nanoseconds later, the control logic causes those cells 28 that are in column 27 to store the instantaneous updated values of all the input signals. This sampling repeats continuously at times t.sub.2, t.sub.3, etc., until the last column of cells in the SCAMs 14, 15, etc., are filled. At that time, the control logic repeats, causing the multichannel analog memory 12 to write the new instantaneous values of the analog signals in the column 26 cells, etc., the data sampling process repeating endlessly.
The multichannel analog memory 12 thus acts as a circular buffer, continuously storing the latest values of the signal information from all the signal sources or detectors. As is well known, all of the sampled values in a column 26, 27, etc., are time-correlated since they are all taken at the same instant of time, and represent time-sampled values of the analog inputs from the detectors or signal sources.
In the collider example, pedestal noise is any noise that is inherent in the analog memories with no preamplifiers attached to them. Pedestal noise is caused from many things but they are all on-chip. The two most common sources of pedestal noise are the cell-to-cell variations which can be random in nature (and cannot be corrected with the present invention), and systematic sources such as the address lines that select the columns (pattern noise). There is also the inherent noise of the cell itself, but that is typically so low it is unmeasured.
In general, then, the pedestals are on-chip internally-caused noise sources, and common-mode is externally caused from power supply variations or preamplifier pickup.
Differential common-mode cancellation has been widely used for common-mode noise subtraction in electronic apparatus. It has also been applied to individual switched-capacitor analog memories, and it has been proposed for large pipelined SCAM systems. In the known embodiments of differential common-mode cancellation applied to SCAMs, one differential element is always used to correct one SCAM. The usual embodiment is one differential amplifier providing a fixed reference offset voltage, or charge (depending on the application) to the output of one SCAM at readout of that SCAM.
In the standard embodiment of differential common-mode cancellation then, just as many reference channel elements (usually differential amplifiers) are required to provide the correction as there are signal channels. Thus, whether applied to systems with one or multiple SCAMs, all of the known forms of differential common-mode cancellation may be termed fully differential common-mode cancellation. The present invention is an alternate method of doing differential common-mode cancellation that requires fewer differential elements than signal channels. The present invention, therefore, will be understood not as another embodiment of fully differential common-mode cancellation, but rather as a new embodiment of differential common-mode cancellation.
The RHIC is expected to use greater than 300,000 analog memory channels, and the standard fully-differential form of common-mode correction is not desired because, at the rate of one reference channel per data channel, an additional 300,000 channels of electronics would be needed. This would increase the silicon real estate, and add greatly to the cost of the detector instrumentation.
The following references provide further description of analog memories, problems of their use, error correction methods, and collider detector analog memory instrumentation.
1. J. T. Walker et al, "Microstore--The Stanford Analog Memory Unit," IEEE Trans. Nuc. Sci., Vol. NS-32, No. 1, pp. 616-621, Feb. 1985. PA1 2. W. Sippach et al, "Development of the Front End Electronics for the ZEUS High Resolution Calorimeter," IEEE Trans. Nuc. Sci., NS-36, pp. 465-470, Feb. 1989. PA1 3. B. Wadsworth, "Technology-Independent Design Considerations for Switched-Capacitor Analog Memories," M.I.T., Laboratory of Nuclear Science Electronics Facility Technical Note 89-6, June 1989. PA1 4. A. Konstantinidis and B. Wadsworth, "Design Considerations for Switched-Capacitor Analog Memories", Laboratory for Nuclear Science, M.I.T.; 1991 Nuclear Science Symposium and Medical Imaging Conference Record, pp. 606-610, Nov. 2-9, 1991.